1. Technical Field
The present invention relates in general to a system and method for increasing the speed of serially inputting data into a JTAG-compliant device. In particular, the present invention relates to a system and a method for inputting data into the device through the control (TMS) line as well as through the data input (TDI) line.
2. Description of the Related Art
Joint Test Action Group (JTAG), or IEEE Standard 1149.1, is a standard specifying how to identify, control, test, and monitor JTAG-compliant devices (such as microprocessors, memory, etc.) on a printed circuit board. Each JTAG-compliant device, in addition to the device's own communication lines, has five additional lines for supporting the JTAG protocol. The lines include a clock (TCK) line, a control (TMS) line for controlling the operation of the device's JTAG-related components, and a common reset (TRST) for resetting the JTAG-portion of the device. In addition, the lines include a data input (TDI) line for serially inputting data into the device and an output data (TDO) line for daisy chaining one device's data output to another's data input.
Internally, a JTAG-compliant device contains a test access protocol (TAP) controller, a state machine whose state is controlled by the signal received on the control (TMS) line. By traversing the different states of the test access protocol (TAP) controller, data can be loaded into and read from internal data and instruction registers, typically for the purpose of determining the proper operation of the device. For example, an instruction can be loaded, followed by data which is processed according to the loaded instruction. For more details on the JTAG-IEEE 1149.1 specification, please refer to IEEE's website.
According to the JTAG specification, the inputting of data into the test access protocol (TAP) controller and the outputting of data out of the test access protocol (TAP) controller is limited to data on the input (TDI) and output (TDO) lines, respectively. Data on these lines flows at the rate of one bit every clock cycle. In cases where many JTAG operations are required and/or many JTAG-compliant devices exist on a printed circuit board, this limitation can significantly increase the time required to run tests or other JTAG-related procedures. Data compression techniques can be used in order to increase the data flow, but such approaches tend to be complex and difficult to implement.
What is needed, therefore, is a system and method that increases the rate at which data can be inputted into a JTAG-compliant device. The system and method should provide the capability to increase the data rate without significantly increasing complexity. At the same time, the operation of the device should remain within the IEEE JTAG protocol in order not to preclude testing of the device using other JTAG-compliant methods.